A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology

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Reference:
A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology (), In J. Solid-State Circuits, volume 49, 2014.
Bibtex Entry:
@article{DBLP:journals/jssc/GangasaniHBBKXFPGRCHBGFEHSM14,
  author    = {Gautam R. Gangasani and
               Chun{-}Ming Hsu and
               John F. Bulzacchelli and
               Troy J. Beukema and
               William Kelly and
               Hui H. Xu and
               David Freitas and
               Andrea Prati and
               Daniele Gardellini and
               Robert Reutemann and
               Giovanni Cervelli and
               Juergen Hertle and
               Matthew Baecher and
               Jon Garlett and
               Pier Andrea Francese and
               John F. Ewen and
               David Hanson and
               Daniel W. Storaska and
               Mounir Meghelli},
  title     = {A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency
               {CDR} in 32 nm {SOI} {CMOS} Technology},
  journal   = {J. Solid-State Circuits},
  volume    = {49},
  number    = {11},
  pages     = {2474--2489},
  year      = {2014},
  url       = {https://doi.org/10.1109/JSSC.2014.2340574},
  doi       = {10.1109/JSSC.2014.2340574},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/jssc/GangasaniHBBKXFPGRCHBGFEHSM14},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}